The present invention relates generally to translator circuits, and more specifically, to emitter coupled logic (ECL) to transistor-transistor logic (TTL) tristate buffer circuits for receiving tristate signals and ECL voltage level input signals and for generating tristated TTL voltage level output signals.
TTL circuitry and ECL circuitry are two well known types of digital circuitry for use in computers and other logic devices. In TTL circuitry a binary "1" is represented by high voltage level between 2.5 and 5 volts, and a binary "0" is represented by a low voltage level between 0 and 0.8 volts. TTL circuitry is generally known for operating at high speed and having low power requirements.
ECL circuitry generally operates at negative voltage with the high and low level voltage signal established on either side of a desired negative reference voltage. For example, if a reference voltage is -1.16 volts, a binary "1" may be represented by a voltage level of -0.8 volts and a binary "0" may be represented by voltage level of -1.5 volts. ECL circuitry is generally known for higher speed switches.
To obtain the advantages of employing both ECL and TTL circuitry on a single integrated circuit or in a system using many circuits, translators are required for translating the binary data from the ECL voltage level to the TTL voltage level.
Multiple translators may be used in more complex circuitry and devices. However, each translator will require a separate communications bus unless the communications translators are multiplexed. In multiplexing, only one translator sharing a bus is generating a signal while the remaining translators are in a high impedance mode. Therefore, each translator sharing a bus must be a tristated translator having three signals (high, low, and high impedance).